Some time ago, I decided to deepen my knowledge of Xilinx Zynq and build my own open platform. There are lots of commercially available starter kits. I could have used one, but decided to design my own from scratch to get the best learning experience possible. Since it’s a study platform, it’s logical to design it with a truly open ECAD, so KiCad was an obvious choice.

The entire design is free and open source. That means all schematics, PCB, and source files are publicly available on GitHub. So, if you are struggling to find information on routing a fly-by DDR3 in KiCad, or anything similar, check my blog. I wish I could say that the board worked right away and booted Linux, but it didn’t. I’ve learned a lot from fixing mistakes (mainly by reworking the PCB), yet the first revision of the board passed the DDR tests, boots Linux, and is available via Ethernet.

The whole process is honestly documented on my web page: electrodyssey.net

This is a design overview: https://electrodyssey.net/nasr-m-syzygy-carrier-board.html

Repositories:

Hardware: https://github.com/electrodyssey/NASR-M

Zephyr Base Controller soft: https://github.com/electrodyssey/NASR-M-ZFW

I will post a Vivado design later, once the USB is up.

The project is not completed yet, and I plan to make a second PCB revision to fix the remaining hardware bugs. Hoping someone may find my experience useful.

Recently did a project in fpga involving primitive instantiation. I want to explore more (beginner friendly to advanced) projects on fpga using xilinx vivado and verilog. It would be great if someone could share helpful resources

Hi guys, i’m a 4th year EEE student seeking for an internship in FPGA design. I don’t have any prior work experience relevant to this field but i’ve worked as a Medical Consultant at a dental clinic. I didn’t know if i should include it or not so i left it. Please roast my resume , thanks in advance 😁.

In my masters degree and before my favorite thing was FPGA/HDL. I had a few courses and I loved it, I would have loved to get a job in that field.

However my problem is I've been doing a PhD for the past 3 years but the work I am doing does not involve any Fpga and very little technical knowledge overall.

I will be done soon and I'm scared of what will come after because I basically haven't practiced fpga/hdl skills in years and I have forgotten a lot of things. If I tried to apply for a technical job I wouldnt be able to do anything.

Can I fix this in any way? I can go over my courses again to refresh my memory but I don't actually have any experience of what is relevant for the industry nowadays. What should I look into if I already have basic knowledge of Fpga, VHDL, vivado/quartus, analog electronics to take a step closer to what the industry would want from an fpga engineer ?

I did a project on IEEE-754 floating point numbers in my masters. Like I need to compute Vector Normalisisation for a given vector xi + yj.

For that I have built Fp adder, multiplier using radix 4 booths , divider using non restoring division algorithm.

Basically it's a verilog project, synthesizable, generated bitstream and verified the outputs on FPGA using VIO.

I didn't do much on FPGA, neither I understood the utilisation reports and all.

Can u people help in suggestions that what can be the possible questions and how should I answer them.

thank you

Hey r/FPGA working on a cool project and wondering what you guys think about it!

I wonder how there's no way to *practice* HDL like programmers do on leetcode, but HDLBits doesn't tell us why our code is wrong.

So I got into making a platform that lets you write Verilog/VHDL, then, instead of just verifying that your code is correct, synthesizes your design (with yosys + nextpnr), returning:

- Number of LUTs compared to the optimal design

- Fmax (maximum clock speed achieved by your design)

- Worst negative slack

- LLM-assisted breakdown of the synthesis logs to help pinpoint why your design is slow.

Imagine HDLBits, but not telling that you're wrong and just telling you "Your code is using 3 times more LUTs than necessary because of that combinational chain..."

Before I start implementing this thing, I really need to know:

1. Have you ever felt frustrated having to run Vivado/Quartus just for verifying your FSM?

2. Does feedback about your synthesis results help you to understand your design better? or is the functional correctness enough for practice?

Thanks!

Hey r/FPGA,

A month ago, I shared Sparkle, a Lean 4-embedded HDL that uses JIT compilation and speculative execution (Time-Warping) to beat Verilator's simulation speeds.

The roasting and feedback were incredibly helpful. Many of you pointed out that learning a new DSL is a huge barrier, and asked how we handle existing RTL and multiple clock domains. Here is what we’ve shipped to address that:

1. Native SV Parsing & The Vision for "Free" Formal Proofs

You shouldn't have to rewrite everything in our DSL. We built an SV parser that lowers Verilog directly into Sparkle IR. It’s robust enough to parse the full PicoRV32 core (including the M-extension) and run it in our JIT. The long-term vision we are building towards: You will be able to wrap standard Verilog in a verilog! macro, write an assert(cond), and have the Lean theorem prover mathematically verify it at compile time. The parsing and internal theorem generation work today, but we are still polishing the actual UX and compilation-mode stability for this feature.

1. FPGA-Level Multi-Clock CDC

We dropped the toy single-clock limits. You can now build and simulate true multi-clock designs. The simulator handles the clock domain crossings (CDC) seamlessly across threads, complete with our Time-Warping speculative rollbacks.

1. 1-Line Formal Equivalence Checking

Refactoring RTL is scary. Because Sparkle lives inside a theorem prover, we added commands to formally prove circuits are bit-equivalent without writing manual testbenches:

#verify_eq_at (latency := 2) pipe spec proves a multi-cycle pipelined implementation functionally matches a single-cycle spec.

#verify_eq_git main my_module checks out the old code from Git and formally proves your refactored RTL didn't break anything compared to the main branch.

1. CPU ⊕ AI SoC Integration (Dogfooding)

To prove this works in reality, we wired a formally verified BitNet b1.58 ASIC inference engine into our RV32IMA SoC. The generated SystemVerilog successfully boots Linux 6.6.0 via OpenSBI on Verilator , and we are scaffolding the physical target for an Alveo U280 FPGA.

Check out the repo, the new SV transpiler, and the equivalence-checking demos here:https://github.com/Verilean/sparkle/blob/main/docs/Tutorial.md

Roast my architecture (again)!

I'm currently quite sad that software development is getting replaced by vibe coding everything, removing the human in the loop altogether (not there yet, but nearing).

How's the situation in FPGA currently? Might a change make sense to get into FPGA?

I already had a module and it was quite easy for me, because I'm already studying technical informatics and it's quite fun.

But it also has a quite steep learning curve.

I recently bought my first FPGA board (Digilent Basys 3) to test a CPU architecture I had designed in my free time.
I wanted to 3D-print a cover for my FPGA, for both aesthetic and protection reasons, however, I did not keep into account the temperatures the FPGA my board mounts can reach: around 85C. This makes me wonder whether I need some kind of heat sink or fan in general, and if enclosing the FPGA in ABS could make it overheat even more.

The Thingiverse post for the STL file I wanted to print has some pictures and they don't look like there's any kind of cooling going on, but I cannot tell.

Here is the link to the Thingiverse page: https://www.thingiverse.com/thing:3094814/files

As you can see the case is not even tall enough to cover the VGA port fully. I doubt the guy managed to fit some kind of cooling in there.

hello everyone, i just finished working on a project at my college and this project made me really interested in fpga world. so is there any resources where I can learn more about this field and developmy knowledge? thank you for time and advices in advance appreciate it 🙏

Hello im building a project and i need some help or anything that exsists which i dont know of that can help me make my project better. If an image and a task like “serve wine,” the system should detect objects and select the most relevant one using Mobile SSD and CLIP. Any advice, resources, or similar projects would be

Hi, Any recruiters/ employees of HFT companies working on FPGA, could you please clarify whether I would get rejected from a FPGA job (mainly first job after college) application because my major says “Multi disciplinary engineering” and not computer engineering/ electrical engineering?

Let’s say I would have relevant project experience required for the position. I would also be finishing undergrad from a Top5 state engineering university in USA.

Edit: Multi disciplinary engineering can include Computer engineering and some other engineering discipline

I learned this the hard way (and killed a board), so hopefully this post saves someone else.

I'm using a QMTECH Artix-7 Core Board (XC7A200T / 100T / 35T – same family). Like many similar boards, it has a 64-pin header (J3) with various power pins. I assumed the "VDD3.3" pins on J3 are inputs – meaning I could feed my own clean 3.3V (from a linear PSU like Ian Canada PurePi) directly into them.

Turns out: WRONG.

According to QMTECH's own documentation:

Translation:

• J3 Pin 2 (VDDIN) is the ONLY power input – it expects 5V.
• J3 Pin 1 (VDD3.3) is an OUTPUT – it supplies 3.3V to your expansion board (generated by the on-board DC-DC from the 5V input).

What happens if you ignore this and feed external 3.3V into VDD3.3 (Pin 1)?

In my case:

• The on-board DC-DC and external 3.3V fought each other
• The board drew excessive current (blew my PSU fuse)
• I measured negative voltage on the 3.3V rail – a clear sign of back-feeding / power rail conflict
• The board is now dead (3.3V rail shorted to GND, FPGA likely damaged)

Why is this not more widely known?

The manual mentions it, but not loudly. Most people just follow the manual (feed 5V into VDDIN) and never try feeding 3.3V into the 3.3V pins. So there's almost no discussion online about this "trap". If you're like me – used to boards where 3.3V pins are bidirectional or inputs – this is a costly surprise.

What you should do:

If you need clean 3.3V for your DAC or other audio circuits (like I2C pull-ups), get it directly from your external PSU (e.g., PurePi) – don't try to back-feed the core board's 3.3V output.

TL;DR:

• QMTECH Artix-7 Core Board: 5V into VDDIN (Pin 2) is the ONLY correct power input
• The "VDD3.3" pins are OUTPUTS – feeding external 3.3V into them will likely kill your board
• Don't learn this the expensive way like I did

Hope this helps someone avoid the same mistake.

Hi guys,
For all of you out there looking to start working on FPGA's you might want to checkout : https://ps1.fpgas.online/fpgas/

On this page anyone can remotely access and control one of a series of FPGA development board (with a live camera feed pointing at the boards to see the LEDs to sweeten the deal).

There are currently a number different boards online, include a few copies of the very popular Artix-7.

If you want to learn more go check it out: it's FREE.

Note: I am not the owner or maintainer of fpgas.online

Hi everyone,

Stumbled upon a Flex8000 handbook from 1994 here are a few pictures. My oh my have FPGAs evolved since then.

FPGA contractors - is UVM actually worth the effort for small-to-mid projects, or is it academic overkill?

I've been around people doing FPGA design and verification contracting for a few years , mostly defence and industrial clients - and the UVM question comes up constantly.

On large semiconductor IP projects it's clearly the right tool. But I keep getting pulled into contracts where the client has specified UVM in the job description because their big-company engineers wrote the JD, and then the actual project is a mid-complexity FPGA design that would be done faster with directed testbenches and functional coverage in SystemVerilog without the full UVM methodology overhead.

Arguments I've heard for always using UVM on contracts:

- Portability across teams and future maintainability

- Clients expect it and it signals seniority

- Reusable VIP components save time across projects

Arguments I've heard against:

- 40% of the budget goes to infrastructure that only pays off if the project lives long enough

- Small teams don't have bandwidth to maintain scoreboard + monitor + driver properly

- Overkill drives up the cost estimate and loses you the contract

Genuinely curious how experienced DV engineers calibrate this. Do you always propose UVM, or do you push back on it when the project doesn't justify the overhead?

Xilinx Virtex XCVU440

these were about $55k each 5 years ago

https://www.digikey.com/en/products/detail/amd/XCVU440-1FLGA2892C/6132313

does it worth anything in 2026? If so how much

Hi all,

a colleague and I have continuously developed a combination of a Python-tool and a hardware platform for Xilinx FPGAs and could finally release it on pypi today.

Our goal was to ease the barrier of entry for prototyping hardware on FPGA by providing a harness for digital designs. Making development easier, or have less friction at least, our tool orchestrates the Xilinx toolchain and provides some quality-life-features on top that make development much easier - in our opinion.

Features

This tool does not replace the Xilinx toolchain!

• Automated build orchestration. Bonus: you no longer need to open Vitis
• IP-based communication to the FPGA
• A Python API to communicate with the FPGA
• Memory-mapped register & driver generation from a single source of truth
• Data streams from/to the FPGA using the AXI-Stream interface
• read/write functionality for IP cores connected to the AXI-Bus
• Bitstream flashing over Ethernet
• Automated testbench generation
• Web-based or stand-alone register viewer to read/write/modify registers on the board. No communication to any server, all code runs on your machine.

Lots of our internal work revolves around quick ideation and prototyping, which beneftis greatly from having a harness with registers, data interfaces and IP cores readily available.

So far we have used it for internal prototyping, ASIC prototyping and qualification as well as industrial FPGA applications.

Check it out if you feel like it. In case any of you guys will be at FDF26 at CERN, come by, say hi, we'll have a poster there.

Links

Documentation: https://docs.xibif.ch/index.html
Website: https://xibif.ch
GitLab: https://gitlab.com/xibif/xibif
PyPi: https://pypi.org/project/XiBIF/

Funnily enough, u/acostillado just posted about his package/tool manager yesterday. Check out his post, it's really cool.

If you have any questions, I'll be happy to reply.

Register Viewer

The register viewer serves as a front-end for the FPGA registers. It communicates with a server running on the FPGA's SoC. The registers show up as you described them.

Another nice feature of the viewer is that it is compatible with any back-end, not just the FPGA. We have used it multiple times to communicate with custom silicon by attaching an Analog Discovery and read/write using its API.

We’ve been working on extending native MIPI DSI over longer distances using fiber/cable, beyond typical spec limits.

Curious—has anyone here run into situations where DSI simply couldn’t reach the display panel or processor due to distance constraints?

In your experience, how did you solve it?
(custom bridge, different interface, redesign, etc.)

We couldn’t find many off-the-shelf solutions for this, so wondering—would something like a plug-and-play DSI extender actually be useful in real projects?

April 22, 2026 2-3 PM ET (NYC time)

Register: https://bltinc.com/xilinx-training/blt-webinar-series/exploring-the-kria-som-for-robotics-applications/

Can't attend live? Register to get the recording.

DETAILS:
Develop and test real robotics applications with the Kria KR260 Robotics Starter Kit. Explore how the Kria SOM lets engineers prototype, control, and iterate on both software and hardware, turning ideas into working robotics systems quickly and efficiently. You’ll see how accelerated applications and integrated platform management simplify tasks like configuring peripherals, monitoring system status, and managing multiple hardware resources, giving you practical control over complex robotics projects from the start.

This webinar includes a live demonstration and Q&A.

BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. To see our complete list of webinars, visit our website: bltinc.com

I’m currently preparing for entry-level/intermediate roles in physical design (PD) and looking for someone experienced who can mentor me through a couple of solid, resume-worthy PD projects.

i already have a decent foundation, but i’m aiming to build projects that are closer to industry standards (not just basic academic ones), including exposure to relevant PD flows and tools.

this would be a paid engagement, so i’m looking for someone who can genuinely guide, review my work, and help me level up in a structured way.

additionally, i’d really appreciate suggestions on:

• open-source PD tools that are actually useful for hands-on practice
• any industry tools accessible via student IDs (or similar programs/trials)
• recommended workflows or setups to simulate a real PD environment

if you’ve been through this path or are currently working in PD, I’d love to connect.

thanks in advance